Discrete logarithmic pseudorandom number generators are a prevailing class of cryptographically-secure pseudorandom number generators (CSPRNGs). In generators of this type, the security parameter affects both security and performance. This adds to the design complexity via creating a critical tradeoff between security and performance. This research is an attempt at shifting the security-performance tradeoff paradigm in this realm. To this end, we propose a modification to Gennaro's pseudorandom number generator via replacing word-wise arithmetic operations with bit-wise logical operations in trapdoor and hard-core functions. The security of our generator (like that of Gennaro's) is based on the hardness of a special variant of the discrete logarithm problem. We establish an equivalence between the specific variant of the discrete logarithm problem with the standard problem. Moreover, we demonstrate that in the modified generator, performance will be almost independent of the security parameter as logical operations can be performed in register level without the interference of the Arithmetic-Logic Unit (ALU). This relaxes the security-performance tradeoff and allows designers to maneuver more flexibly in the tradeoff space. We implement and evaluate our proposed generator and prove its security. Our CSPRNG is deemed random by all randomness tests in NIST SP 800-22 suite.
ASJC Scopus subject areas
- コンピュータ ネットワークおよび通信