A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter

Shuai Shao; Youhua Shi; Wentao Dai; Jianyi Meng; Weiwei Shan

doi:10.1109/EDSSC.2015.7285066

A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter

Shuai Shao, Youhua Shi, Wentao Dai, Jianyi Meng, Weiwei Shan^*

^*この研究の対応する著者

基幹理工学部

研究成果: Conference contribution

抄録

A universal delay monitor used to imitate the real critical paths is developed for variation resilient integrated circuit. This monitor is constructed based on the different proportion of logic cells and interconnects. The delay of the monitor is detected by a time-to-digital converter which keeps the sampling results precise. To reduce the deviation of the sampling results caused by PVT, a novel time-to-digital converter with self-calibration mechanism is developed. This variation resilient method based adaptive voltage scaling is applied on an ARM7 based System on a Chip on 0.18 μm CMOS process with a 112M signoff frequency and an area of 1.3∗1.3 mm². The simulation results show that it has a 43.42% gain of power consumption under FF corner, -25°C compared to the fixed 1.8 V traditional design.

本文言語	English
ホスト出版物のタイトル	Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	126-129
ページ数	4
ISBN（電子版）	9781479983636
DOI	https://doi.org/10.1109/EDSSC.2015.7285066
出版ステータス	Published - 2015 9月 30
イベント	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore 継続期間: 2015 6月 1 → 2015 6月 4

出版物シリーズ

名前	Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

Other

Other	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
国/地域	Singapore
City	Singapore
Period	15/6/1 → 15/6/4

ASJC Scopus subject areas

電子工学および電気工学

文献へのアクセス

10.1109/EDSSC.2015.7285066

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引用スタイル

Shao, S., Shi, Y., Dai, W., Meng, J., & Shan, W. (2015). A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 126-129). 記事 7285066 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285066

A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. / Shao, Shuai; Shi, Youhua; Dai, Wentao その他.
Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 126-129 7285066 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015).

研究成果: Conference contribution

Shao, S, Shi, Y, Dai, W, Meng, J & Shan, W 2015, A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. in Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015., 7285066, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 126-129, 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Singapore, Singapore, 15/6/1. https://doi.org/10.1109/EDSSC.2015.7285066

Shao S, Shi Y, Dai W, Meng J, Shan W. A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 126-129. 7285066. (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015). doi: 10.1109/EDSSC.2015.7285066

Shao, Shuai ; Shi, Youhua ; Dai, Wentao その他. / A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 126-129 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015).

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abstract = "A universal delay monitor used to imitate the real critical paths is developed for variation resilient integrated circuit. This monitor is constructed based on the different proportion of logic cells and interconnects. The delay of the monitor is detected by a time-to-digital converter which keeps the sampling results precise. To reduce the deviation of the sampling results caused by PVT, a novel time-to-digital converter with self-calibration mechanism is developed. This variation resilient method based adaptive voltage scaling is applied on an ARM7 based System on a Chip on 0.18 μm CMOS process with a 112M signoff frequency and an area of 1.3∗1.3 mm2. The simulation results show that it has a 43.42% gain of power consumption under FF corner, -25°C compared to the fixed 1.8 V traditional design.",

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AU - Shan, Weiwei

N1 - Funding Information: Acknowledgment: This paper is supported by Qinglan Project and Open Research funding of State Key Laboratory of ASIC and System, Fudan University (2015KF010). Publisher Copyright: © 2015 IEEE.

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N2 - A universal delay monitor used to imitate the real critical paths is developed for variation resilient integrated circuit. This monitor is constructed based on the different proportion of logic cells and interconnects. The delay of the monitor is detected by a time-to-digital converter which keeps the sampling results precise. To reduce the deviation of the sampling results caused by PVT, a novel time-to-digital converter with self-calibration mechanism is developed. This variation resilient method based adaptive voltage scaling is applied on an ARM7 based System on a Chip on 0.18 μm CMOS process with a 112M signoff frequency and an area of 1.3∗1.3 mm2. The simulation results show that it has a 43.42% gain of power consumption under FF corner, -25°C compared to the fixed 1.8 V traditional design.

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A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter

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