A VLSI array processing oriented fast fourier transform algorithm and hardware implementation

Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. One FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2^k butterfly units (BUs) could be scheduled to work in parallel on n = 2^s data (k = 0, 1,⋯, s - 1). Because no inter stage data transfer is required, memory consumption and system latency are both greatly reduced. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. In theory, the system latency is (s × 2^s-k) × t_clk and the throughput is n/(s x 2^s-k × t_clk), where t_clk is the system clock period. Based on this mapping algorithm, several 18-bit word-length 1024-point FFT processors implemented with TSMC0.18μm CMOS technology are given to demonstrate its scalability and high performance. The core area of 4-BU design is 2.991 × 1.121 mm² and clock frequency is 326 MHz in typical condition (1.8 V, 25°C). This processor completes 1024 FFT calculation in 7.839 μs.