TY - GEN
T1 - Accurate measurement of sneak current in reram crossbar array with data storage pattern dependencies
AU - Shang, Yaqi
AU - Ohsawa, Takashi
N1 - Funding Information:
This work was supported by VLSI Design and Education Center (VDEC), The University of Tokyo with collaboration with Cadence Corporation and Synopsys Corporation.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/4
Y1 - 2019/4
N2 - In this paper, readout scheme in ReRAM crossbar array based on sneak current compensation is introduced. This scheme consists of two cycles. In the first measurement cycle, an accurate sneak current is measured which is dependent on the data storage patterns of the crossbar arrays in which the selector ON/OFF ratio is not large enough. In the second cycle, the measured sneak current is subtracted from the total bit line current to predict the cell current accurately. To make the measured sneak current accurate, the crossbar array is divided into many blocks only in one direction so that the impact of array size increase is minimal. The scheme is validated by using HSPICE.
AB - In this paper, readout scheme in ReRAM crossbar array based on sneak current compensation is introduced. This scheme consists of two cycles. In the first measurement cycle, an accurate sneak current is measured which is dependent on the data storage patterns of the crossbar arrays in which the selector ON/OFF ratio is not large enough. In the second cycle, the measured sneak current is subtracted from the total bit line current to predict the cell current accurately. To make the measured sneak current accurate, the crossbar array is divided into many blocks only in one direction so that the impact of array size increase is minimal. The scheme is validated by using HSPICE.
KW - Reram CBA
KW - compensation
KW - data storage pattern dependency
KW - sneak current
UR - http://www.scopus.com/inward/record.url?scp=85072132511&partnerID=8YFLogxK
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U2 - 10.1109/VLSI-TSA.2019.8804668
DO - 10.1109/VLSI-TSA.2019.8804668
M3 - Conference contribution
AN - SCOPUS:85072132511
T3 - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
BT - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Y2 - 22 April 2019 through 25 April 2019
ER -