All-wet fabrication process for ULSI interconnect technologies

M. Yoshino, Y. Nonaka, J. Sasano, I. Matsuda, Y. Shacham-Diamand, T. Osaka*


研究成果: Article査読

61 被引用数 (Scopus)


"All-wet process" for fabrication of Cu wiring on a silicon chip was proposed as a novel ultra-large scale integration (ULSI) interconnect technology for integrated circuits (ICs) applications. Electroless-NiB film was deposited on SiO2/Si substrate modified by self-assembled-monolayer (SAM) activated with PdCl2. The NiB film formed by this method has highly uniform, with good adhesion to the substrate and with good diffusion barrier characteristics against Cu diffusion. Cu was electrodeposited directly on the electroless NiB film that acted as a seed layer. This was done without any conventional conductive or adhesive layer that is conventionally formed by physical vapor deposition (PDV). The thermal stability of electroless NiB layer as a barrier preventing copper from diffusing into the SiO2/Si substrate was evaluated by secondary ion mass spectroscopy (SIMS) and sheet resistance measurement at several annealing temperatures. It was confirmed that the electroless NiB film blocked Cu diffusion and kept the layer integrity under annealing temperatures of up to 400 °C for 30 min. The same process of electroless NiB was used for the capping layer that was also formed by "wet process", as the electroless NiB film deposited selectively onto a surface of Cu wiring was also applicable to a capping layer. We conclude that the proposed process is very promising for sub-100 nm technologies as it offers a variety of desirable properties: it has good step coverage while showing good barrier and seed layer properties.

ジャーナルElectrochimica Acta
出版ステータスPublished - 2005 11月 10

ASJC Scopus subject areas

  • 化学工学(全般)
  • 電気化学


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