An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler

Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Masaki Ito; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; Jun Shirako; Masayoshi Mase; Keiji Kimura; Hironori Kasahara

doi:10.1109/ISSCC.2008.4523071

An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler

Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Masaki Ito, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

基幹理工学部

研究成果: Conference contribution

37 被引用数 (Scopus)

抄録

A 104.8mm² 90nm CMOS 600MHz SoC integrates 8 processor cores and 8 user RAMs in 17 separate power domains and delivers 33.6GFLOPS. An automatic parallelizing compiler assigns tasks to each CPU and controls its power mode including power supply in accordance with its processing load and status. The compiler also uses barrier registers to achieve fast and accurate CPU synchronization.

本文言語	English
ホスト出版物のタイトル	2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	89-91
ページ数	3
ISBN（印刷版）	9781424420100
DOI	https://doi.org/10.1109/ISSCC.2008.4523071
出版ステータス	Published - 2008
イベント	2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States 継続期間: 2008 2月 3 → 2008 2月 7

出版物シリーズ

名前	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
巻	51
ISSN（印刷版）	0193-6530

Conference

Conference	2008 IEEE International Solid State Circuits Conference, ISSCC
国/地域	United States
City	San Francisco, CA
Period	08/2/3 → 08/2/7

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

文献へのアクセス

10.1109/ISSCC.2008.4523071

他のファイルとリンク

引用スタイル

Ito, M., Hattori, T., Yoshida, Y., Hayase, K., Hayashi, T., Nishii, O., Yasu, Y., Hasegawa, A., Takada, M., Ito, M., Mizuno, H., Uchiyama, K., Odaka, T., Shirako, J., Mase, M., Kimura, K., & Kasahara, H. (2008). An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC (pp. 89-91). [4523071] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2008.4523071

An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler. / Ito, Masayuki; Hattori, Toshihiro; Yoshida, Yutaka その他.
2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc., 2008. p. 89-91 4523071 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51).

研究成果: Conference contribution

Ito, M, Hattori, T, Yoshida, Y, Hayase, K, Hayashi, T, Nishii, O, Yasu, Y, Hasegawa, A, Takada, M, Ito, M, Mizuno, H, Uchiyama, K, Odaka, T, Shirako, J, Mase, M, Kimura, K & Kasahara, H 2008, An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler. in 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC., 4523071, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 51, Institute of Electrical and Electronics Engineers Inc., pp. 89-91, 2008 IEEE International Solid State Circuits Conference, ISSCC, San Francisco, CA, United States, 08/2/3. https://doi.org/10.1109/ISSCC.2008.4523071

Ito M, Hattori T, Yoshida Y, Hayase K, Hayashi T, Nishii O その他. An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc. 2008. p. 89-91. 4523071. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2008.4523071

Ito, Masayuki ; Hattori, Toshihiro ; Yoshida, Yutaka その他. / An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler. 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. Institute of Electrical and Electronics Engineers Inc., 2008. pp. 89-91 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler

抄録

出版物シリーズ

Conference

ASJC Scopus subject areas

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