TY - GEN
T1 - An adder-segmentation-based FIR for high speed signal processing
AU - Ye, Jinghao
AU - Yanagisawa, Masao
AU - Shi, Youhua
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - An advanced adder-segmentation-based FIR filter design for high speed signal processing is proposed in this paper. In the proposed method, the critical path delay is shortened through adder segmentation. An analysis for the optimization of adder segmentation is also proposed, which can be used for critical path delay balance to maximize the performance of FIR filters. The evaluation results show that the proposed design can achieve up to 30.7% and 22.8% reduction in area-delay-product (ADP) and energy-delay-product (EDP) when compared with the existing FIR filters.
AB - An advanced adder-segmentation-based FIR filter design for high speed signal processing is proposed in this paper. In the proposed method, the critical path delay is shortened through adder segmentation. An analysis for the optimization of adder segmentation is also proposed, which can be used for critical path delay balance to maximize the performance of FIR filters. The evaluation results show that the proposed design can achieve up to 30.7% and 22.8% reduction in area-delay-product (ADP) and energy-delay-product (EDP) when compared with the existing FIR filters.
UR - http://www.scopus.com/inward/record.url?scp=85082593906&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85082593906&partnerID=8YFLogxK
U2 - 10.1109/ASICON47005.2019.8983612
DO - 10.1109/ASICON47005.2019.8983612
M3 - Conference contribution
AN - SCOPUS:85082593906
T3 - Proceedings of International Conference on ASIC
BT - Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
A2 - Ye, Fan
A2 - Tang, Ting-Ao
PB - IEEE Computer Society
T2 - 13th IEEE International Conference on ASIC, ASICON 2019
Y2 - 29 October 2019 through 1 November 2019
ER -