抄録
The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings - IEEE International Symposium on Circuits and Systems |
ページ | 1712-1715 |
ページ数 | 4 |
DOI | |
出版ステータス | Published - 2013 |
イベント | 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing 継続期間: 2013 5月 19 → 2013 5月 23 |
Other
Other | 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 |
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City | Beijing |
Period | 13/5/19 → 13/5/23 |
ASJC Scopus subject areas
- 電子工学および電気工学