TY - GEN
T1 - An Area-efficient Unified Transform Architecture for VVC
AU - Hao, Zhijian
AU - Zheng, Qi
AU - Fan, Yibo
AU - Xiang, Guoqing
AU - Zhang, Peng
AU - Sun, Heming
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported in part by the National Natural Science Foundation of China under Grant 62031009, in part by the Shanghai Science and Technology Committee (STCSM) under Grant 19511104300, in part by Alibaba Innovative Research (AIR) Program, in part by the Innovation Program of Shanghai Municipal Education Commission, in part by the Fudan University-CIOMP Joint Fund(FC2019-001), in part by the Fudan-ZTE Joint Lab, in part by Pioneering Project of Academy for Engineering and Technology Fudan University(gyy2021-001), in part by JST, PRESTO Grant Number JPMJPR19M5, in part by JSPS KAKENHI under Grant 21K17770.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The next-generation video coding standard Versatile Video Coding (VVC) adopts Multiple Transform Selection (MTS) to the transform module, improving coding efficiency at the expense of high computational complexity. Compared to High Efficiency Video Coding (HEVC), VVC supports larger sizes and extends the transform types to Discrete Cosine Transform (DCT)-II, Discrete Sine Transform (DST)-VII, and DCT-VIII. This paper presents an area-efficient unified architecture for VVC. To reduce the area consumption, we propose an optimized calculation scheme for general transformations where the transform matrix is decomposed into two simpler matrices named the Low-value matrix and the Error matrix. Based on the decomposition algorithm, Shift-Addition Units (SAUs)-based circuits are designed to conduct matrix multiplication and can be reused by three types. As a result, this unified architecture is capable of performing all types and sizes in VVC. The synthesis results indicate that this architecture achieves an area reduction of 37.9% sim 72.2% compared with related works for 32-point transforms.
AB - The next-generation video coding standard Versatile Video Coding (VVC) adopts Multiple Transform Selection (MTS) to the transform module, improving coding efficiency at the expense of high computational complexity. Compared to High Efficiency Video Coding (HEVC), VVC supports larger sizes and extends the transform types to Discrete Cosine Transform (DCT)-II, Discrete Sine Transform (DST)-VII, and DCT-VIII. This paper presents an area-efficient unified architecture for VVC. To reduce the area consumption, we propose an optimized calculation scheme for general transformations where the transform matrix is decomposed into two simpler matrices named the Low-value matrix and the Error matrix. Based on the decomposition algorithm, Shift-Addition Units (SAUs)-based circuits are designed to conduct matrix multiplication and can be reused by three types. As a result, this unified architecture is capable of performing all types and sizes in VVC. The synthesis results indicate that this architecture achieves an area reduction of 37.9% sim 72.2% compared with related works for 32-point transforms.
KW - area-efficient
KW - optimized calculation scheme
KW - SAUs-based matrix multiplication
KW - unified architecture
KW - Versatile Video Coding
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U2 - 10.1109/ISCAS48785.2022.9937709
DO - 10.1109/ISCAS48785.2022.9937709
M3 - Conference contribution
AN - SCOPUS:85142502268
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2012
EP - 2016
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Y2 - 27 May 2022 through 1 June 2022
ER -