Nowdays, Low-power design, especially Multi-voltage design becomes a popular and efficient way to reduce both dynamic power and static power. In this paper, we propose an efficient method of level-shifter floorplanning for a given multi-voltage design. This method is a two stage optimization method. First, for a given voltage island and its sequence pair representation, we greedily pre-place level-shifters into white-spaces of multi-voltage island based sequence-pair representation. Then, we employ a modified IARFP  algorithm to re-optimize the positions of level-shifters. Experimental results show that, the proposed two stage level-shifter floorplanner is efficient for post multi-voltage island optimization.
|ホスト出版物のタイトル||Proceedings of International Conference on ASIC|
|出版ステータス||Published - 2011|
|イベント||2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen|
継続期間: 2011 10月 25 → 2011 10月 28
|Other||2011 IEEE 9th International Conference on ASIC, ASICON 2011|
|Period||11/10/25 → 11/10/28|
ASJC Scopus subject areas