TY - GEN
T1 - An efficient deadlock-free adaptive routing algorithm for 3D network-on-chips
AU - Dai, Jindun
AU - Jiang, Xin
AU - Li, Renjie
AU - Watanabe, Takahiro
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/2
Y1 - 2017/7/2
N2 - Network-on-Chips (NoC) has been proven as a flexible solution for Chip-Multiprocessor (CMP) systems due to its reusability and scalability. To increase communication efficiency, Three-Dimensional Networks-on-Chips (3D NoCs) are developed, which can shorten the wire length and improve the system performance. In this paper, we present a novel deadlock-free adaptive routing algorithm for 3D mesh NoC interconnections. The routing rules of traditional XY routing and YX routing are relaxed and used for intra-layer routing. Via multiple layers, balanced adaptiveness can be achieved. We detail the basic principle of this method and test its efficiency through simulations.
AB - Network-on-Chips (NoC) has been proven as a flexible solution for Chip-Multiprocessor (CMP) systems due to its reusability and scalability. To increase communication efficiency, Three-Dimensional Networks-on-Chips (3D NoCs) are developed, which can shorten the wire length and improve the system performance. In this paper, we present a novel deadlock-free adaptive routing algorithm for 3D mesh NoC interconnections. The routing rules of traditional XY routing and YX routing are relaxed and used for intra-layer routing. Via multiple layers, balanced adaptiveness can be achieved. We detail the basic principle of this method and test its efficiency through simulations.
KW - 3D network-on-chip
KW - adaptive routing
KW - computer architecture
KW - multiprocessing systems
UR - http://www.scopus.com/inward/record.url?scp=85049727676&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85049727676&partnerID=8YFLogxK
U2 - 10.1109/MCSoC.2017.10
DO - 10.1109/MCSoC.2017.10
M3 - Conference contribution
AN - SCOPUS:85049727676
T3 - Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
SP - 29
EP - 36
BT - Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
Y2 - 18 September 2017 through 20 September 2017
ER -