An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Lingfeng Li; Satoshi Goto; Takeshi Ikenaga

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Lingfeng Li^*, Satoshi Goto, Takeshi Ikenaga

^*この研究の対応する著者

大学院情報生産システム研究科

研究成果: Conference contribution

22 被引用数 (Scopus)

抄録

In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

本文言語	English
ホスト出版物のタイトル	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
ページ	623-626
ページ数	4
出版ステータス	Published - 2005 12月 1
イベント	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China 継続期間: 2005 1月 18 → 2005 1月 21

出版物シリーズ

名前	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
巻	1

Conference

Conference	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
国/地域	China
City	Shanghai
Period	05/1/18 → 05/1/21

ASJC Scopus subject areas

コンピュータサイエンスの応用
コンピュータグラフィックスおよびコンピュータ支援設計
電子工学および電気工学

他のファイルとリンク

引用スタイル

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. / Li, Lingfeng; Goto, Satoshi; Ikenaga, Takeshi.
Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. p. 623-626 1466238 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

研究成果: Conference contribution

Li, L, Goto, S & Ikenaga, T 2005, An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466238, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, pp. 623-626, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 05/1/18.

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abstract = "In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.",

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AB - In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

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M3 - Conference contribution

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T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

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T2 - 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

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An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

抄録

出版物シリーズ

Conference

ASJC Scopus subject areas

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