This paper presents a majority-logic based message-passing algorithm for decoding non-binary LDPC codes. Recently, many majority-logic decoding (MLGD) algorithms make huge efforts on reducing the computational complexity for decoding non-binary LDPC codes. Inspired by one step majority-logic decoding and q-ary sum-product algorithm, we devise a novel iterative double-reliability- based (IDRB) MLGD algorithm which carries out an efficient trade-off between decoding computational complexity and error performance. The proposed algorithm achieves a remarkable enhancement on error correct ability and yet requires only integer operations and finite field operations. Simulation results on two NB-LDPC codes show that we succeed in achieving significant coding gain compared with IHRB-and ISRB-MLGD with limited complexity increase.
|ホスト出版物のタイトル||IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS|
|出版ステータス||Published - 2012|
|イベント||2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung|
継続期間: 2012 12月 2 → 2012 12月 5
|Other||2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012|
|Period||12/12/2 → 12/12/5|
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