An Experimental 4-Mbit CMOS DRAM

Tohru Furuyama; Takashi Ohsawa; Yohji Watanabe; Hidemi Ishiuchi; Toshiharu Watanabe; Takeshi Tanaka; Kenji Natori; Osamu Ozawa

doi:10.1109/JSSC.1986.1052584

An Experimental 4-Mbit CMOS DRAM

Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Hidemi Ishiuchi, Toshiharu Watanabe, Takeshi Tanaka, Kenji Natori, Osamu Ozawa

研究成果: Article › 査読

25 被引用数 (Scopus)

抄録

A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

本文言語	English
ページ（範囲）	605-611
ページ数	7
ジャーナル	IEEE Journal of Solid-State Circuits
巻	21
号	5
DOI	https://doi.org/10.1109/JSSC.1986.1052584
出版ステータス	Published - 1986 10月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/JSSC.1986.1052584

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引用スタイル

@article{fdbd11e11ac64e9b87a08989336812d6,

title = "An Experimental 4-Mbit CMOS DRAM",

abstract = "A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.",

author = "Tohru Furuyama and Takashi Ohsawa and Yohji Watanabe and Hidemi Ishiuchi and Toshiharu Watanabe and Takeshi Tanaka and Kenji Natori and Osamu Ozawa",

year = "1986",

month = oct,

doi = "10.1109/JSSC.1986.1052584",

language = "English",

volume = "21",

pages = "605--611",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - An Experimental 4-Mbit CMOS DRAM

AU - Furuyama, Tohru

AU - Ohsawa, Takashi

AU - Watanabe, Yohji

AU - Ishiuchi, Hidemi

AU - Watanabe, Toshiharu

AU - Tanaka, Takeshi

AU - Natori, Kenji

AU - Ozawa, Osamu

PY - 1986/10

Y1 - 1986/10

N2 - A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

AB - A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

UR - http://www.scopus.com/inward/record.url?scp=11644258099&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=11644258099&partnerID=8YFLogxK

U2 - 10.1109/JSSC.1986.1052584

DO - 10.1109/JSSC.1986.1052584

M3 - Article

AN - SCOPUS:11644258099

SN - 0018-9200

VL - 21

SP - 605

EP - 611

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 5

ER -

An Experimental 4-Mbit CMOS DRAM

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