An FPGA-based 4K UHDTV H.264/AVC video decoder

Yue Pan; Dajiang Zhou; Satoshi Goto

doi:10.1109/ICMEW.2013.6618319

An FPGA-based 4K UHDTV H.264/AVC video decoder

Yue Pan, Dajiang Zhou, Satoshi Goto

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.

本文言語	English
ホスト出版物のタイトル	Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013
DOI	https://doi.org/10.1109/ICMEW.2013.6618319
出版ステータス	Published - 2013
イベント	2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013 - San Jose, CA 継続期間: 2013 7月 15 → 2013 7月 19

Other

Other	2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013
City	San Jose, CA
Period	13/7/15 → 13/7/19

ASJC Scopus subject areas

コンピュータグラフィックスおよびコンピュータ支援設計
コンピュータビジョンおよびパターン認識

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10.1109/ICMEW.2013.6618319

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引用スタイル

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title = "An FPGA-based 4K UHDTV H.264/AVC video decoder",

abstract = "An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.",

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AB - An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported.

KW - 4K UHDTV

KW - DRAM bandwidth

KW - FPGA

KW - H.264/AVC

KW - HDMI displaying

KW - video decoder

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BT - Electronic Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2013

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Y2 - 15 July 2013 through 19 July 2013

ER -

An FPGA-based 4K UHDTV H.264/AVC video decoder

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