抄録
FRC (frame re-compression) is a kind of widely used technique in reducing the SDRAM (synchronous dynamic random access memory) bandwidth of HEVC video system. However, in previous research works, FRC imposes requirements on accessing pattern and hence its usage are only limited in HEVC video codecs. While in a typical HEVC VLSI video system, there exists many other video IPs with high bandwidth requirements. Therefore, in this article, we propose a new FRC architecture to overcome the limitation and make it applicable to all the video IPs in a HEVC VLSI video system, which raises the overall bandwidth reduction rate of the whole video system. Our proposal has two points: firstly we propose a system internal bus based FRC architecture, which is independent, transparent, and easily connected to all other video IPs. Secondly, we propose a FA (freely access) scheme to remove the requirements on access pattern in previous work. By using this proposal, the bandwidth reduction rate in our VLSI video system model is raised from 92.4% to 69.6%.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings - IEEE International Symposium on Circuits and Systems |
| 出版社 | Institute of Electrical and Electronics Engineers Inc. |
| ページ | 609-612 |
| ページ数 | 4 |
| 巻 | 2015-July |
| ISBN（印刷版） | 9781479983919 |
| DOI | |
| 出版ステータス | Published - 2015 7月 27 |
| イベント | IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal 継続期間: 2015 5月 24 → 2015 5月 27 |
Other
| Other | IEEE International Symposium on Circuits and Systems, ISCAS 2015 |
|---|---|
| 国/地域 | Portugal |
| City | Lisbon |
| Period | 15/5/24 → 15/5/27 |
ASJC Scopus subject areas
- 電子工学および電気工学