An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

Shin Ichiro Kimura; Yoshifumi Kawamoto; Norio Hasegawa; Atsushi Hiraiwa; Yoshinobu Nakagome; Masakazu Aoki; Hideo Sunami; Kiyoo Itoh; Teruaki Kisu

doi:10.1109/16.7358

An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

Shin Ichiro Kimura, Yoshifumi Kawamoto, Norio Hasegawa, Atsushi Hiraiwa, Yoshinobu Nakagome, Masakazu Aoki, Hideo Sunami, Kiyoo Itoh, Teruaki Kisu

研究成果: Article › 査読

6 被引用数 (Scopus)

抄録

A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM’s.

本文言語	English
ページ（範囲）	1591-1595
ページ数	5
ジャーナル	IEEE Transactions on Electron Devices
巻	35
号	10
DOI	https://doi.org/10.1109/16.7358
出版ステータス	Published - 1988
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学
電子材料、光学材料、および磁性材料

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10.1109/16.7358

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@article{fdf6b337e21b4fdeb2035407c3d2c376,

title = "An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell",

abstract = "A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM{\textquoteright}s.",

author = "Kimura, {Shin Ichiro} and Yoshifumi Kawamoto and Norio Hasegawa and Atsushi Hiraiwa and Yoshinobu Nakagome and Masakazu Aoki and Hideo Sunami and Kiyoo Itoh and Teruaki Kisu",

year = "1988",

doi = "10.1109/16.7358",

language = "English",

volume = "35",

pages = "1591--1595",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

AU - Kimura, Shin Ichiro

AU - Kawamoto, Yoshifumi

AU - Hasegawa, Norio

AU - Hiraiwa, Atsushi

AU - Nakagome, Yoshinobu

AU - Aoki, Masakazu

AU - Sunami, Hideo

AU - Itoh, Kiyoo

AU - Kisu, Teruaki

PY - 1988

Y1 - 1988

N2 - A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM’s.

AB - A 4.2-µm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-µm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM’s.

UR - http://www.scopus.com/inward/record.url?scp=84941510775&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84941510775&partnerID=8YFLogxK

U2 - 10.1109/16.7358

DO - 10.1109/16.7358

M3 - Article

AN - SCOPUS:84941510775

SN - 0018-9383

VL - 35

SP - 1591

EP - 1595

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 10

ER -

An Optically Delineated 4.2-µm2Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell

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