Approximate multiplier using reordered 4-2 compressor with or-based error compensation

Today, the approximate circuits have become an efficient solution for low power design on human related error-tolerant applications, such as multimedia, recognition and several signal processing. Approximate multipliers are believed to be an important key to make approximate arithmetic systems, and more area efficient multiplier is expected. The paper proposes a new ar-ea-efficient 4-2 compressor based on input reordering and OR-based error compensation. By the reordering, we can focus on just 2 of 4 inputs, and the compressor becomes very simple and less gates. Two multipliers are proposed with different accuracy based on reordered compressors with OR-based error compensation. The experimental results show that the proposed multipliers achieve high accuracy (98.7% and 97.39%) while reduce power consumption (by 44.72% and 45.95%) and area (by 31.72% and 34.85%). The proposed approximate multipliers are applied on image sharpening process and show high PSNR and SSIM.