@inproceedings{809bdc2398e64fc9a991de3019c88fd6,
title = "ASIC CAD system based on hierarchical design-for-testability",
abstract = "The authors propose a novel test CAD (computer-aided-design) system for ASIC (application-specific integrated circuits), including megacells which automatically insert high-testability logic. The strategy is to access megacells directly and independently. The overhead is only 2% to 3% of the total number of gates. With the proposed system, hierarchically designed logic data can be converted to high-testability logic. It is not necessary for the designers to have specialized knowledge about design-for-testability.",
author = "Michiaki Emori and Takashi Aikyo and Yasuhide Machida and Shikatani, {Jun ichi}",
year = "1990",
month = sep,
language = "English",
isbn = "0818620641",
series = "Digest of Papers - International Test Conference",
publisher = "Publ by IEEE",
pages = "404--409",
booktitle = "Digest of Papers - International Test Conference",
note = "Proceedings - International Test Conference 1990 ; Conference date: 10-09-1990 Through 14-09-1990",
}