@inproceedings{57c28c5a2df6472d9f1a16abdc55ee7f,
title = "At-speed testing with timing exceptions and constraints -case studies",
abstract = "In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in [1][2]. The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism.",
keywords = "At-speed test, False paths, Multicycle paths, Static timing analysis (STA), Synopsys design constraints (SDC), Timing constraints, Timing exceptions",
author = "Dhiraj Goswami and Tsai, {Kun Han} and Mark Kassab and Takeo Kobayashi and Janusz Rajski and Bruce Swanson and Darryl Walters and Yasuo Sato and Toshiharu Asaka and Takashi Aikyo",
year = "2006",
doi = "10.1109/ATS.2006.261014",
language = "English",
isbn = "0769526284",
series = "Proceedings of the Asian Test Symposium",
pages = "153--159",
booktitle = "Proceedings of the 15th Asian Test Symposium 2006",
note = "15th Asian Test Symposium 2006 ; Conference date: 20-11-2006 Through 23-11-2006",
}