ATREX: Design for Testability System for Mega Gate LSIs

Michiaki Emori; Junko Kumagai; Koichi Itaya; Takashi Aikyo; Tomoko Anan; Junichi Niimi

ATREX: Design for Testability System for Mega Gate LSIs

Michiaki Emori^*, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi

^*この研究の対応する著者

研究成果: Conference article › 査読

抄録

We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.

本文言語	English
ページ（範囲）	126-129
ページ数	4
ジャーナル	Proceedings of the Asian Test Symposium
出版ステータス	Published - 1997
外部発表	はい
イベント	Proceedings of the 1997 6th Asian Test Symposium - Akita, Jpn 継続期間: 1997 11月 17 → 1997 11月 19

ASJC Scopus subject areas

電子工学および電気工学

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引用スタイル

@article{f0d6b70c5fe44ce696d7f5ae83bcf85b,

title = "ATREX: Design for Testability System for Mega Gate LSIs",

abstract = "We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.",

author = "Michiaki Emori and Junko Kumagai and Koichi Itaya and Takashi Aikyo and Tomoko Anan and Junichi Niimi",

year = "1997",

language = "English",

pages = "126--129",

journal = "Proceedings of the Asian Test Symposium",

issn = "1081-7735",

publisher = "IEEE Computer Society",

note = "Proceedings of the 1997 6th Asian Test Symposium ; Conference date: 17-11-1997 Through 19-11-1997",

}

TY - JOUR

T1 - ATREX

T2 - Proceedings of the 1997 6th Asian Test Symposium

AU - Emori, Michiaki

AU - Kumagai, Junko

AU - Itaya, Koichi

AU - Aikyo, Takashi

AU - Anan, Tomoko

AU - Niimi, Junichi

PY - 1997

Y1 - 1997

N2 - We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.

AB - We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.

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UR - http://www.scopus.com/inward/citedby.url?scp=0031380770&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0031380770

SN - 1081-7735

SP - 126

EP - 129

JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

Y2 - 17 November 1997 through 19 November 1997

ER -

ATREX: Design for Testability System for Mega Gate LSIs

抄録

ASJC Scopus subject areas

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