With the increase in the density and gate count of LSI and VLSI, test pattern generation becomes more and more difficult. One solution to this problem is scan path design. This paper describes an automatic test generation system for scan path design that has been applied to CMOS 20K gate arrays at Fujitsu. A feature of this system is automatic test generation for logic circuits with on-chip RAM, bidirectional buses, and clock control circuits using a time expanded modeling method and an extended PODEM algorithm with 17 signal values.