TY - JOUR
T1 - Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis
AU - Doi, Nobuhiro
AU - Horiyama, Takashi
AU - Nakanishi, Masaki
AU - Kimura, Shinji
AU - Watanabe, Katsumasa
PY - 2003/12
Y1 - 2003/12
N2 - In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.
AB - In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.
KW - Bit length
KW - HDL
KW - High-level synthesis
KW - Parallelizing compiler
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M3 - Article
AN - SCOPUS:0842332224
SN - 0916-8508
VL - E86-A
SP - 3184
EP - 3191
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 12
ER -