Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

Xiao Xu; Xin Yang; Taufiq Alif Kurniawan; Toshihiko Yoshimasu

doi:10.1109/EDSSC.2015.7285200

Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

Xiao Xu, Xin Yang, Taufiq Alif Kurniawan, Toshihiko Yoshimasu

大学院情報生産システム研究科

研究成果: Conference contribution

抄録

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

本文言語	English
ホスト出版物のタイトル	Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	653-655
ページ数	3
ISBN（印刷版）	9781479983636
DOI	https://doi.org/10.1109/EDSSC.2015.7285200
出版ステータス	Published - 2015 9月 30
イベント	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore 継続期間: 2015 6月 1 → 2015 6月 4

Other

Other	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
国/地域	Singapore
City	Singapore
Period	15/6/1 → 15/6/4

ASJC Scopus subject areas

電子工学および電気工学

文献へのアクセス

10.1109/EDSSC.2015.7285200

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引用スタイル

Xu, X., Yang, X., Kurniawan, T. A., & Yoshimasu, T. (2015). Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 653-655). [7285200] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285200

Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS. / Xu, Xiao; Yang, Xin; Kurniawan, Taufiq Alif その他.
Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 653-655 7285200.

研究成果: Conference contribution

Xu, X, Yang, X, Kurniawan, TA & Yoshimasu, T 2015, Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS. in Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015., 7285200, Institute of Electrical and Electronics Engineers Inc., pp. 653-655, 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Singapore, Singapore, 15/6/1. https://doi.org/10.1109/EDSSC.2015.7285200

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title = "Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS",

abstract = "This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.",

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author = "Xiao Xu and Xin Yang and Kurniawan, {Taufiq Alif} and Toshihiko Yoshimasu",

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doi = "10.1109/EDSSC.2015.7285200",

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N2 - This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5-dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

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Broadband highly linear high isolation SPDT switch IC with floating body technique in 180-nm CMOS

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Other

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