Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high-speed, low soft error rate and low power consumption.
|ジャーナル||Electronics & communications in Japan|
|出版ステータス||Published - 1983 7月|
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