Circuit design of reconfigurable logic based on double-gate CNTFETs

Manabu Kobayashi, Hiroshi Ninomiya, Shigeyoshi Watanabe

研究成果: Article査読

3 被引用数 (Scopus)

抄録

I. O'Connor et al. have proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) to generate some logic functions by using the double-gate (DG) carbon nanotube (CNT) FETs which have the ambipolar property [1]. This DRDLC consists of seven transistors to generate 14 logic functions which do not include the XOR and XNOR functions. On the other hand, K. Jabeur et al. have proposed a DRDLC to generate the whole set of 16 logic functions including XOR and XNOR by adding 4 or 8 transistors to O'Connor's circuit [5]. In this letter, we propose a DRDLC, which consists of only seven transistors, to generate the whole set of 16 logic functions by using DG-CNTFETs. Finally, we show that the number of transistors can be reduced compared to the conventional DRDLC to generate 16 logic functions.

本文言語English
ページ(範囲)1642-1644
ページ数3
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E96-A
7
DOI
出版ステータスPublished - 2013 7月
外部発表はい

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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