Clock skew estimate modeling for FPGA high-level synthesis and its application

Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/ASICON.2015.7516905

Clock skew estimate modeling for FPGA high-level synthesis and its application

Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.

本文言語	English
ホスト出版物のタイトル	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781479984831
DOI	https://doi.org/10.1109/ASICON.2015.7516905
出版ステータス	Published - 2016 7月 19
イベント	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China 継続期間: 2015 11月 3 → 2015 11月 6

Other

Other	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
国/地域	China
City	Chengdu
Period	15/11/3 → 15/11/6

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/ASICON.2015.7516905

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引用スタイル

Fujiwara, K, Kawamura, K, Yanagisawa, M & Togawa, N 2016, Clock skew estimate modeling for FPGA high-level synthesis and its application. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7516905, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7516905

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abstract = "Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.",

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AU - Fujiwara, Koichi

AU - Kawamura, Kazushi

AU - Yanagisawa, Masao

AU - Togawa, Nozomu

PY - 2016/7/19

Y1 - 2016/7/19

N2 - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.

AB - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.

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DO - 10.1109/ASICON.2015.7516905

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BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 3 November 2015 through 6 November 2015

ER -

Clock skew estimate modeling for FPGA high-level synthesis and its application

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