Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi; Kenichi Imamiya; Koji Sakui

doi:10.1109/TEPM.2000.895053

Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi^*, Kenichi Imamiya, Koji Sakui

^*この研究の対応する著者

研究成果: Article › 査読

抄録

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n⁺ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

本文言語	English
ページ（範囲）	235
ページ数	1
ジャーナル	IEEE Transactions on Electronics Packaging Manufacturing
巻	23
号	4
DOI	https://doi.org/10.1109/TEPM.2000.895053
出版ステータス	Published - 2000
外部発表	はい

ASJC Scopus subject areas

産業および生産工学
電子工学および電気工学

文献へのアクセス

10.1109/TEPM.2000.895053

他のファイルとリンク

引用スタイル

@article{c29f96bcdbf84b8db430859fe7bc56cb,

title = "Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory",

abstract = "With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.",

author = "Tamio Ikehashi and Kenichi Imamiya and Koji Sakui",

year = "2000",

doi = "10.1109/TEPM.2000.895053",

language = "English",

volume = "23",

pages = "235",

journal = "IEEE Transactions on Electronics Packaging Manufacturing",

issn = "1521-334X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

AU - Ikehashi, Tamio

AU - Imamiya, Kenichi

AU - Sakui, Koji

PY - 2000

Y1 - 2000

N2 - With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

AB - With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

UR - http://www.scopus.com/inward/record.url?scp=33747987735&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33747987735&partnerID=8YFLogxK

U2 - 10.1109/TEPM.2000.895053

DO - 10.1109/TEPM.2000.895053

M3 - Article

AN - SCOPUS:33747987735

SN - 1521-334X

VL - 23

SP - 235

JO - IEEE Transactions on Electronics Packaging Manufacturing

JF - IEEE Transactions on Electronics Packaging Manufacturing

IS - 4

ER -

Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

抄録

ASJC Scopus subject areas

文献へのアクセス

他のファイルとリンク

フィンガープリント

引用スタイル