TY - GEN
T1 - Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory
AU - Ikehashi, Tamio
AU - Imamiya, Kenichi
AU - Sakui, Koji
PY - 1999/12/1
Y1 - 1999/12/1
N2 - With the use of a device simulator, it is shown that an electrostatic discharge (ESD) protection circuit whose junction filled with contacts is suited to a scaled shallow trench isolation (STI) process having thin n- junction with n+ being implanted from contact holes. It is confirmed by measurements that the protection has sufficient robustness.
AB - With the use of a device simulator, it is shown that an electrostatic discharge (ESD) protection circuit whose junction filled with contacts is suited to a scaled shallow trench isolation (STI) process having thin n- junction with n+ being implanted from contact holes. It is confirmed by measurements that the protection has sufficient robustness.
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M3 - Conference contribution
AN - SCOPUS:0033279726
SN - 158537007X
T3 - Electrical Overstress/Electrostatic Discharge Symposium Proceedings
SP - 225
EP - 234
BT - Electrical Overstress/Electrostatic Discharge Symposium Proceedings
PB - ESD Assoc
T2 - Proceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge'
Y2 - 28 September 1999 through 30 September 1999
ER -