Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier

Yi Guo, Heming Sun, Shinji Kimura

研究成果: Conference contribution

13 被引用数 (Scopus)


Approximate computing has been paid attention as a promising technique to decrease power and area for error-tolerant applications by simplifying the internal operations with sacrificing their accuracy. In this paper, a new power and area efficient approximate multiplier is proposed using OR based compressor with no carry propagation for lower bit positions and a carry propagation compressor with inexact half adders and full adders for upper bit positions. The proposal is effective to reduce the critical path delay with almost the same precision with previous methods. Firstly, an inexact half adder and an inexact full adder are proposed and a construction method of 4×4 multiplier is shown. Then, a construction method of 8×8 multiplier is proposed using OR based compressor, approximate 4×4 multipliers and an accurate 4×4 multiplier. The proposed construction method can also be applied to 16×16 multiplier. The accuracy loss of proposed multipliers is evaluated using MATLAB simulation and that of the proposed 8×8 multiplier is low as 0.20%, the effect of which is shown to be negligible by applying to discrete cosine transform (DCT), inverse DCT and convolutional neural networks for image classification. The proposed 8×8 multiplier reduces power and area by 50.78% and 53.19%, respectively, compared with the accurate Wallace tree multiplier when evaluated using SMIC 40nm process.

ホスト出版物のタイトルProceedings of TENCON 2018 - 2018 IEEE Region 10 Conference
出版社Institute of Electrical and Electronics Engineers Inc.
出版ステータスPublished - 2019 2月 22
イベント2018 IEEE Region 10 Conference, TENCON 2018 - Jeju, Korea, Republic of
継続期間: 2018 10月 282018 10月 31


名前IEEE Region 10 Annual International Conference, Proceedings/TENCON


Conference2018 IEEE Region 10 Conference, TENCON 2018
国/地域Korea, Republic of

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学


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