Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Akiyuki Nagashima; Yuta Imai; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1109/APCCAS.2008.4746121

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Akiyuki Nagashima^*, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

^*この研究の対応する著者

基幹理工学部

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Recently a demand for high-speed wireless network service on mobile devices is rapidly increasing. Error correcting codes are used to enhance network communication quality. Particularly, LDPC (Low Density Parity Check) codes show high throughput and achieve information rates very close to the Shannon limit. In this paper, we propose a dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. Our proposed decoder deals with multi-rate codes by introducing a multi-rate compatible 1st-2nd minimum searching unit. The proposed decoder shows the better throughput over the wide range of S/N ratio compared to conventional rate-fixed LDPC decoders.

本文言語	English
ホスト出版物のタイトル	Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
ページ	705-708
ページ数	4
DOI	https://doi.org/10.1109/APCCAS.2008.4746121
出版ステータス	Published - 2008 12月 1
イベント	APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China 継続期間: 2008 11月 30 → 2008 12月 3

出版物シリーズ

名前	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
国/地域	China
City	Macao
Period	08/11/30 → 08/12/3

ASJC Scopus subject areas

電子工学および電気工学

文献へのアクセス

10.1109/APCCAS.2008.4746121

他のファイルとリンク

引用スタイル

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2008). Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. In Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (pp. 705-708). [4746121] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2008.4746121

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. / Nagashima, Akiyuki; Imai, Yuta; Togawa, Nozomu その他.
Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. 2008. p. 705-708 4746121 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

Nagashima, A, Imai, Y, Togawa, N , Yanagisawa, M & Ohtsuki, T 2008, Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. in Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems., 4746121, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 705-708, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, 08/11/30. https://doi.org/10.1109/APCCAS.2008.4746121

Nagashima A, Imai Y, Togawa N , Yanagisawa M, Ohtsuki T. Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. In Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. 2008. p. 705-708. 4746121. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). doi: 10.1109/APCCAS.2008.4746121

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Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

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出版物シリーズ

Conference

ASJC Scopus subject areas

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