In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance C eff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation.
|ホスト出版物のタイトル||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版ステータス||Published - 2005|
|イベント||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
継続期間: 2005 5月 23 → 2005 5月 26
|Other||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005|
|Period||05/5/23 → 05/5/26|
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