TY - GEN
T1 - Effective post-BIST fault diagnosis for multiple faults
AU - Takahashi, Hiroshi
AU - Kadoyama, Shuhei
AU - Higami, Yoshinobu
AU - Takamatsu, Yuzo
AU - Yamazaki, Koji
AU - Aikyo, Takashi
AU - Sato, Yasuo
PY - 2006
Y1 - 2006
N2 - With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.
AB - With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.
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U2 - 10.1109/DFT.2006.24
DO - 10.1109/DFT.2006.24
M3 - Conference contribution
AN - SCOPUS:38749113382
SN - 076952706X
SN - 9780769527062
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SP - 109
EP - 117
BT - Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Y2 - 4 October 2006 through 6 October 2006
ER -