Efficient data-path synthesis based on algorithmic description under the constraints of time and area

The major purpose of this paper is to present a general redesigning methodology, which is able to optimize the circuit area and processing speed simultaneously under the constraints of time and area at a speed of O(nlog(n)). Our methodology first designs the most serial data-path with the smallest area, and then, repeats the stepwise modification of the data-path based on an efficient redesigning method employing the Time-Area ratio (T-A ratio in short) until a nearly optimized one is obtained.