TY - GEN
T1 - Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors
AU - Guo, Yi
AU - Sun, Heming
AU - Kimura, Shinji
N1 - Funding Information:
Corporation. The work was supported in part by Grants-Aid for Scientific Research from JSPS and a research fund from NEC. The work of Y. Guo was supported by the China Scholarship Council scholarship. The authors convey their sincere gratitude.
Funding Information:
This work was partly executed under the cooperation of organization between Waseda University and Toshiba Memory Corporation. The work was supported in part by Grants-Aid for Scientific Research from JSPS and a research fund from NEC. The work of Y. Guo was supported by the China Scholarship Council scholarship. The authors convey their sincere gratitude.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/9
Y1 - 2019/9
N2 - Approximate computing has emerged as a promising approach to reduce energy by sacrificing some accuracy in error-tolerant applications. For these applications, multiplication is a key fundamental operation. In the paper, we propose an approximate signed multiplier design with a low power consumption and a short critical path. Inexact sign-focused compressors are first proposed to accumulate partial products, which cut the carry propagation and simplify the circuit complexity. Moreover, three types of approximate multipliers are presented to achieve different trade-offs between accuracy loss and hardware saving. Experimental results show that the most accurate proposed multiplier reduces power by 52.44%, area by 37.73%, and delay by 22.14%, compare with the exact signed multiplier. In addition, the proposed multiplier design costs less hardware than other multipliers with a comparable accuracy. At last, an application to image processing shows the efficiency of proposed signed multipliers.
AB - Approximate computing has emerged as a promising approach to reduce energy by sacrificing some accuracy in error-tolerant applications. For these applications, multiplication is a key fundamental operation. In the paper, we propose an approximate signed multiplier design with a low power consumption and a short critical path. Inexact sign-focused compressors are first proposed to accumulate partial products, which cut the carry propagation and simplify the circuit complexity. Moreover, three types of approximate multipliers are presented to achieve different trade-offs between accuracy loss and hardware saving. Experimental results show that the most accurate proposed multiplier reduces power by 52.44%, area by 37.73%, and delay by 22.14%, compare with the exact signed multiplier. In addition, the proposed multiplier design costs less hardware than other multipliers with a comparable accuracy. At last, an application to image processing shows the efficiency of proposed signed multipliers.
KW - Approximate computing
KW - inexact compressor
KW - low power
KW - signed multiplier
UR - http://www.scopus.com/inward/record.url?scp=85085176283&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85085176283&partnerID=8YFLogxK
U2 - 10.1109/SOCC46988.2019.1570548436
DO - 10.1109/SOCC46988.2019.1570548436
M3 - Conference contribution
AN - SCOPUS:85085176283
T3 - International System on Chip Conference
SP - 330
EP - 335
BT - Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019
A2 - Zhao, Danella
A2 - Basu, Arindam
A2 - Bayoumi, Magdy
A2 - Hwee, Gwee Bah
A2 - Tong, Ge
A2 - Sridhar, Ramalingam
PB - IEEE Computer Society
T2 - 32nd IEEE International System on Chip Conference, SOCC 2019
Y2 - 3 September 2019 through 6 September 2019
ER -