Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Shota Matsuno; Masashi Tawada; Masao Yanagisawa; Shinji Kimura; Nozomu Togawa; Tadahiko Sugibayashi

doi:10.1109/ASICON.2013.6811826

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

As leakage power of traditional SRAM becomes larger, a ratio of static energy in total energy of memory architecture becomes also larger. Non-volatile memory (NVM) has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but consumes too much write energy. In this paper, we evaluate energy consumption of two-level cache using NVM in part on mobile processors and confirm that it effectively reduces energy consumption.

本文言語	English
ホスト出版物のタイトル	2013 IEEE 10th International Conference on ASIC, ASICON 2013
出版社	IEEE Computer Society
ISBN（印刷版）	9781467364157
DOI	https://doi.org/10.1109/ASICON.2013.6811826
出版ステータス	Published - 2013 1月 1
イベント	2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen, China 継続期間: 2013 10月 28 → 2013 10月 31

出版物シリーズ

名前	Proceedings of International Conference on ASIC
ISSN（印刷版）	2162-7541
ISSN（電子版）	2162-755X

Other

Other	2013 IEEE 10th International Conference on ASIC, ASICON 2013
国/地域	China
City	Shenzhen
Period	13/10/28 → 13/10/31

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

UN SDG

この成果は、次の持続可能な開発目標に貢献しています

文献へのアクセス

10.1109/ASICON.2013.6811826

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引用スタイル

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N., & Sugibayashi, T. (2013). Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. In 2013 IEEE 10th International Conference on ASIC, ASICON 2013 記事 6811826 (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASICON.2013.6811826

Matsuno, S, Tawada, M , Yanagisawa, M , Kimura, S , Togawa, N & Sugibayashi, T 2013, Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. in 2013 IEEE 10th International Conference on ASIC, ASICON 2013., 6811826, Proceedings of International Conference on ASIC, IEEE Computer Society, 2013 IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, 13/10/28. https://doi.org/10.1109/ASICON.2013.6811826

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AU - Matsuno, Shota

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AU - Togawa, Nozomu

AU - Sugibayashi, Tadahiko

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AB - As leakage power of traditional SRAM becomes larger, a ratio of static energy in total energy of memory architecture becomes also larger. Non-volatile memory (NVM) has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but consumes too much write energy. In this paper, we evaluate energy consumption of two-level cache using NVM in part on mobile processors and confirm that it effectively reduces energy consumption.

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Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

抄録

出版物シリーズ

Other

ASJC Scopus subject areas

UN SDG

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