TY - GEN
T1 - F-LIC
T2 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022
AU - Sun, Heming
AU - Yi, Qingyang
AU - Lin, Fangzheng
AU - Yu, Lu
AU - Katto, Jiro
AU - Fujita, Masahiro
N1 - Funding Information:
This work was supported in part by JST, PRESTO Grant Number JPMJPR19M5, Japan; in part by JSPS, Grant Number 21K17770; in part by Kenjiro Takayanagi Foundation.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Recently, learned image compression (LIC) has shown a superior ability in the compression ratio as well as the quality of the reconstructed image. By adopting the framework of variational autoencoder, LIC [1] can outperform the intra prediction of the latest traditional coding standard VVC. To accelerate the coding speed, most LIC frameworks are operated on GPU with the floating-point arithmetic. However, the mismatch of floating-point calculation results on various hardware platforms will cause the decoding error if encoding and decoding are performed on different platforms. Therefore, LIC with a fixed-point arithmetic [2-3] is highly required. This paper gives an FPGA design for a LIC with 8-bit fixed-point quantization. Different from existing FPGA accelerators [4-6], we propose a fine-grained pipeline architecture to realize high DSP efficiency. Cascading DSP and the deconvolution with zero skipping are also developed to enhance the hardware performance.
AB - Recently, learned image compression (LIC) has shown a superior ability in the compression ratio as well as the quality of the reconstructed image. By adopting the framework of variational autoencoder, LIC [1] can outperform the intra prediction of the latest traditional coding standard VVC. To accelerate the coding speed, most LIC frameworks are operated on GPU with the floating-point arithmetic. However, the mismatch of floating-point calculation results on various hardware platforms will cause the decoding error if encoding and decoding are performed on different platforms. Therefore, LIC with a fixed-point arithmetic [2-3] is highly required. This paper gives an FPGA design for a LIC with 8-bit fixed-point quantization. Different from existing FPGA accelerators [4-6], we propose a fine-grained pipeline architecture to realize high DSP efficiency. Cascading DSP and the deconvolution with zero skipping are also developed to enhance the hardware performance.
UR - http://www.scopus.com/inward/record.url?scp=85146554232&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85146554232&partnerID=8YFLogxK
U2 - 10.1109/A-SSCC56115.2022.9980666
DO - 10.1109/A-SSCC56115.2022.9980666
M3 - Conference contribution
AN - SCOPUS:85146554232
T3 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
BT - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 6 November 2022 through 9 November 2022
ER -