Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

Meishoku Masahara; Takashi Matsukawa; Kenichi Ishii; Yongxun Liu; Masayoshi Nagao; Hisao Tanoue; Takashi Tanii; Iwao Ohdomari; Seigo Kanemaru; Eiichi Suzuki

doi:10.1143/jjap.42.1916

Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

Meishoku Masahara^*, Takashi Matsukawa, Kenichi Ishii, Yongxun Liu, Masayoshi Nagao, Hisao Tanoue, Takashi Tanii, Iwao Ohdomari, Seigo Kanemaru, Eiichi Suzuki

^*この研究の対応する著者

基幹理工学部

研究成果: Article › 査読

12 被引用数 (Scopus)

抄録

It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.

本文言語	English
ページ（範囲）	1916-1918
ページ数	3
ジャーナル	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
巻	42
号	4 B
DOI	https://doi.org/10.1143/jjap.42.1916
出版ステータス	Published - 2003 4月

ASJC Scopus subject areas

工学（全般）
物理学および天文学（全般）

文献へのアクセス

10.1143/jjap.42.1916

他のファイルとリンク

フィンガープリント

「Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル

Masahara, M., Matsukawa, T., Ishii, K., Liu, Y., Nagao, M., Tanoue, H., Tanii, T., Ohdomari, I., Kanemaru, S., & Suzuki, E. (2003). Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 42(4 B), 1916-1918. https://doi.org/10.1143/jjap.42.1916

Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). / Masahara, Meishoku; Matsukawa, Takashi; Ishii, Kenichi その他.
In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 42, No. 4 B, 04.2003, p. 1916-1918.

研究成果: Article › 査読

Masahara, M, Matsukawa, T, Ishii, K, Liu, Y, Nagao, M, Tanoue, H, Tanii, T, Ohdomari, I, Kanemaru, S & Suzuki, E 2003, 'Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)', Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, vol. 42, no. 4 B, pp. 1916-1918. https://doi.org/10.1143/jjap.42.1916

Masahara M, Matsukawa T, Ishii K, Liu Y, Nagao M, Tanoue H その他. Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 2003 4月;42(4 B):1916-1918. doi: 10.1143/jjap.42.1916

Masahara, Meishoku ; Matsukawa, Takashi ; Ishii, Kenichi その他. / Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 2003 ; Vol. 42, No. 4 B. pp. 1916-1918.

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abstract = "It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.",

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author = "Meishoku Masahara and Takashi Matsukawa and Kenichi Ishii and Yongxun Liu and Masayoshi Nagao and Hisao Tanoue and Takashi Tanii and Iwao Ohdomari and Seigo Kanemaru and Eiichi Suzuki",

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AU - Matsukawa, Takashi

AU - Ishii, Kenichi

AU - Liu, Yongxun

AU - Nagao, Masayoshi

AU - Tanoue, Hisao

AU - Tanii, Takashi

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AU - Suzuki, Eiichi

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AB - It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.

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KW - Ion-bombardment-retarded etching of Si

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KW - Ultrathin Si wall

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