Fault-Tolerant traffic-Aware routing algorithm for 3-d photonic networks-on-chip

As the number of cores on a single chip increased, the inter-core communication system quickly became the performance bottleneck. In order to solve the performance and scalability issues of bus-based systems, Network-on-chip (NoC) was proposed. This eventually met its own bottleneck and several technologies sprouted out from NoC research. The most commonly researched upgrade to NoCs was 3D NoCs, which utilized stacked routers to reduce the maximum hop count. Other researchers have looked at alternative transmission mediums, such as photonics. These technologies can be combined to give great performance and power benefits but can be slowed down by congestion in their path-setup phase. In order to solve this issue, we propose a traffic-Aware routing algorithm that can evenly distribute the traffic throughout the chip, all while simultaneously avoiding faulty nodes. The results show that the proposed algorithm was successful in balancing the load across the chip and that the performance costs of the algorithm were mostly offset by the benefits of reducing blocked paths.