Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

Shigenobu Maeda^*, Yoshiki Wada, Kazuya Yamamoto, Hiroshi Komurasaki, Takuji Matsumoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Kimio Ueda, Koichiro Mashiko, Shigeto Maegawa, Masahide Inuishi