TY - JOUR
T1 - Floorplan-driven high-level synthesis for distributed/shared-register architectures
AU - Ohchi, Akira
AU - Kohara, Shunitsu
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2008/8
Y1 - 2008/8
N2 - In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/ FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.
AB - In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/ FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.
UR - http://www.scopus.com/inward/record.url?scp=79954475551&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79954475551&partnerID=8YFLogxK
U2 - 10.2197/ipsjtsldm.1.78
DO - 10.2197/ipsjtsldm.1.78
M3 - Article
AN - SCOPUS:79954475551
SN - 1882-6687
VL - 1
SP - 78
EP - 90
JO - IPSJ Transactions on System LSI Design Methodology
JF - IPSJ Transactions on System LSI Design Methodology
ER -