TY - GEN
T1 - Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems
AU - Asai, Daiki
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/1
Y1 - 2017/7/1
N2 - In this paper, we propose a floorplan-driven highlevel synthesis algorithm utilizing both volatile and non-volatile registers for hybrid energy-harvesting systems. In our algorithm, we firstly introduce an idea of safety line candidates. Based on them, we perform safety-line (SL) scheduling so that every operation does not cross the safety line candidates and then perform volatile/non-volatile register binding so that all the data crossing the safety line candidates are stored into non-violate registers. We can safely restore all the data and re-start the circuit operation from every safety line candidate, even if the power shut-off occurs while running the circuit. Experimental results show that our algorithm reduces average latency by 30.76% and the average energy consumption by 24.94% compared to the naive algorithm when sufficient energy is given (normal mode). Experimental results also show that our algorithm reduces average latency by 30.58% compared to the naive algorithm by reducing rollback execution if a small amount of energy is given (energy-harvesting mode).
AB - In this paper, we propose a floorplan-driven highlevel synthesis algorithm utilizing both volatile and non-volatile registers for hybrid energy-harvesting systems. In our algorithm, we firstly introduce an idea of safety line candidates. Based on them, we perform safety-line (SL) scheduling so that every operation does not cross the safety line candidates and then perform volatile/non-volatile register binding so that all the data crossing the safety line candidates are stored into non-violate registers. We can safely restore all the data and re-start the circuit operation from every safety line candidate, even if the power shut-off occurs while running the circuit. Experimental results show that our algorithm reduces average latency by 30.76% and the average energy consumption by 24.94% compared to the naive algorithm when sufficient energy is given (normal mode). Experimental results also show that our algorithm reduces average latency by 30.58% compared to the naive algorithm by reducing rollback execution if a small amount of energy is given (energy-harvesting mode).
UR - http://www.scopus.com/inward/record.url?scp=85044755941&partnerID=8YFLogxK
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U2 - 10.1109/ASICON.2017.8252412
DO - 10.1109/ASICON.2017.8252412
M3 - Conference contribution
AN - SCOPUS:85044755941
T3 - Proceedings of International Conference on ASIC
SP - 64
EP - 67
BT - Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
A2 - Qin, Yajie
A2 - Hong, Zhiliang
A2 - Tang, Ting-Ao
PB - IEEE Computer Society
T2 - 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
Y2 - 25 October 2017 through 28 October 2017
ER -