Floorplanning for high utilization of heterogeneous FPGAs

Nan Liu*, Song Chen, Takeshi Yoshimura


研究成果: Conference contribution

2 被引用数 (Scopus)


Heterogeneous resources such as configurable logic blocks (CLBs), multiplier blocks (MULs) and ram blocks (RAMs) where millions of logic gates (a growing trend to implement larger and more complex functions) included have been added to field programmable gate arrays (FPGAs). And floorplanning for this, hierarchical approach is recognized as the most effective method. The FPGA architecture shows that CLBs hold the maximum quantity much more than other resources. Therefore, making a high utilization of them means an enhancement of the FPGA densities. This paper presents a three-phase floorplanning method for heterogeneous FPGAs. The proposed method can make the resource requirement of functional modules satisfied with a high resource utilization. First, we use a non-slicing floorplanning method to optimize the wirelength, however, in this phase, the satisfaction of resource requirements from functional modules might fail. Second, a min-cost-max-flow algorithm is used to tune the assignment of CLBs to functional modules, such that all the functional modules get CLB requirements satisfied. Finally, the MULs and RAMs are allocated to modules by a network flow model. The results show that about 7%-85% wirelength reduction is obtained, and CLB utilization is improved by about 25%.

ホスト出版物のタイトルProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
出版ステータスPublished - 2011
イベント12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA
継続期間: 2011 3月 142011 3月 16


Other12th International Symposium on Quality Electronic Design, ISQED 2011
CitySanta Clara, CA

ASJC Scopus subject areas

  • 電子工学および電気工学


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