After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and wirelength may cause design failure for the circuits, because of ignoring some hidden constraints. In this paper, we propose a method to extract some geometric constraints based on interconnecting information analysis. And a new floorplanning algorithm with CBL representation which can handle these constraints is also proposed. And the final experimental results prove the effectiveness of our method.
|ホスト出版物のタイトル||ASICON 2007 - 2007 7th International Conference on ASIC Proceeding|
|出版ステータス||Published - 2007|
|イベント||2007 7th International Conference on ASIC, ASICON 2007 - Guilin|
継続期間: 2007 10月 26 → 2007 10月 29
|Other||2007 7th International Conference on ASIC, ASICON 2007|
|Period||07/10/26 → 07/10/29|
ASJC Scopus subject areas