Floorplanning with constraint extraction based on interconnecting information analysis

Jiayi Liu; Sheqin Dong; Xianlong Hong; Satoshi Goto

doi:10.1109/ICASIC.2007.4415821

Floorplanning with constraint extraction based on interconnecting information analysis

Jiayi Liu^*, Sheqin Dong, Xianlong Hong, Satoshi Goto

^*この研究の対応する著者

早稲田大学

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and wirelength may cause design failure for the circuits, because of ignoring some hidden constraints. In this paper, we propose a method to extract some geometric constraints based on interconnecting information analysis. And a new floorplanning algorithm with CBL representation which can handle these constraints is also proposed. And the final experimental results prove the effectiveness of our method.

本文言語	English
ホスト出版物のタイトル	ASICON 2007 - 2007 7th International Conference on ASIC Proceeding
ページ	1084-1087
ページ数	4
DOI	https://doi.org/10.1109/ICASIC.2007.4415821
出版ステータス	Published - 2007
イベント	2007 7th International Conference on ASIC, ASICON 2007 - Guilin 継続期間: 2007 10月 26 → 2007 10月 29

Other

Other	2007 7th International Conference on ASIC, ASICON 2007
City	Guilin
Period	07/10/26 → 07/10/29

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/ICASIC.2007.4415821

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引用スタイル

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title = "Floorplanning with constraint extraction based on interconnecting information analysis",

abstract = "After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and wirelength may cause design failure for the circuits, because of ignoring some hidden constraints. In this paper, we propose a method to extract some geometric constraints based on interconnecting information analysis. And a new floorplanning algorithm with CBL representation which can handle these constraints is also proposed. And the final experimental results prove the effectiveness of our method.",

author = "Jiayi Liu and Sheqin Dong and Xianlong Hong and Satoshi Goto",

year = "2007",

doi = "10.1109/ICASIC.2007.4415821",

language = "English",

isbn = "1424411327",

pages = "1084--1087",

booktitle = "ASICON 2007 - 2007 7th International Conference on ASIC Proceeding",

note = "2007 7th International Conference on ASIC, ASICON 2007 ; Conference date: 26-10-2007 Through 29-10-2007",

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TY - GEN

T1 - Floorplanning with constraint extraction based on interconnecting information analysis

AU - Liu, Jiayi

AU - Dong, Sheqin

AU - Hong, Xianlong

AU - Goto, Satoshi

PY - 2007

Y1 - 2007

N2 - After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and wirelength may cause design failure for the circuits, because of ignoring some hidden constraints. In this paper, we propose a method to extract some geometric constraints based on interconnecting information analysis. And a new floorplanning algorithm with CBL representation which can handle these constraints is also proposed. And the final experimental results prove the effectiveness of our method.

AB - After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and wirelength may cause design failure for the circuits, because of ignoring some hidden constraints. In this paper, we propose a method to extract some geometric constraints based on interconnecting information analysis. And a new floorplanning algorithm with CBL representation which can handle these constraints is also proposed. And the final experimental results prove the effectiveness of our method.

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U2 - 10.1109/ICASIC.2007.4415821

DO - 10.1109/ICASIC.2007.4415821

M3 - Conference contribution

AN - SCOPUS:48349084098

SN - 1424411327

SN - 9781424411320

SP - 1084

EP - 1087

BT - ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

T2 - 2007 7th International Conference on ASIC, ASICON 2007

Y2 - 26 October 2007 through 29 October 2007

ER -

Floorplanning with constraint extraction based on interconnecting information analysis

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