TY - GEN
T1 - GECOM
T2 - 2008 Asia and South Pacific Design Automation Conference, ASP-DAC
AU - Shi, Youhua
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2008
Y1 - 2008
N2 - This paper introduces GECOM technology, a novel test compression method with seamless integration of test GEneration, test COmpression (i.e. integrated compression on scan stimulus and masking bits) and all unknown scan responses Masking for manufacturing test cost reduction. Unlike most of prior methods, the proposed method considers the unknown responses during ATPG procedure and selectively encodes the specified 1 or 0 bits (either 1s or 0s) in scan slices for compression while at the same time masks the unknown responses before sending them to the response compactor. The proposed GECOM technology consists of GECOM architecture and GECOM ATPG technique. In the GECOM architecture, for a circuit with N internal scan chains, only c tester channels, where c = [log2 N] +2, are required. GECOM ATPG generates test patterns for the GECOM architecture thus not only the scan inputs could be efficiently compressed but also all the unknown responses would be masked. Experimental results on both benchmark circuits and real industrial designs indicated the effectiveness of the proposed GECOM technique.
AB - This paper introduces GECOM technology, a novel test compression method with seamless integration of test GEneration, test COmpression (i.e. integrated compression on scan stimulus and masking bits) and all unknown scan responses Masking for manufacturing test cost reduction. Unlike most of prior methods, the proposed method considers the unknown responses during ATPG procedure and selectively encodes the specified 1 or 0 bits (either 1s or 0s) in scan slices for compression while at the same time masks the unknown responses before sending them to the response compactor. The proposed GECOM technology consists of GECOM architecture and GECOM ATPG technique. In the GECOM architecture, for a circuit with N internal scan chains, only c tester channels, where c = [log2 N] +2, are required. GECOM ATPG generates test patterns for the GECOM architecture thus not only the scan inputs could be efficiently compressed but also all the unknown responses would be masked. Experimental results on both benchmark circuits and real industrial designs indicated the effectiveness of the proposed GECOM technique.
UR - http://www.scopus.com/inward/record.url?scp=49549098340&partnerID=8YFLogxK
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U2 - 10.1109/ASPDAC.2008.4484018
DO - 10.1109/ASPDAC.2008.4484018
M3 - Conference contribution
AN - SCOPUS:49549098340
SN - 9781424419227
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 577
EP - 582
BT - 2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Y2 - 21 March 2008 through 24 March 2008
ER -