TY - GEN
T1 - H.264/AVC fractional motion estimation engine with computation reusing in HDTV1080P real-time encoding applications
AU - Song, Yang
AU - Shao, Ming
AU - Liu, Zhenyu
AU - Li, Shen
AU - Li, Ngfeng
AU - Ikenaga, Takeshi
AU - Goto, Satoshi
PY - 2007/12/1
Y1 - 2007/12/1
N2 - H.264/AVC fractional motion estimation (FME) engine for HDTV 1080p is proposed in this paper. In order to provide real-time processing capability with reasonable hardware cost, several techniques have been presented. Firstly, the H.264/AVC is optimized and only 1 reference frame and block modes above 8 × 8 are supported. Therefore, the computation is reduced to 11.4% and the PSNR loss is only 0.1dB. Secondly, the lossless inside-mode and cross-mode reusing techniques are adopted, which can reduce about 65% pixel generation and SATD calculation. Thirdly, the lossless optimized FME scheduling is used to remove the pipeline bubbles between adjacent 1/2-pel and 1/4-pel FME. The proposed FME engine is realized with TSMC 0.18μm 1P6M CMOS technology and costs 203.2K gates and 52.8KB SRAM. Under 200MHz frequency, the proposed FME engine can real-time encode HDTV 1080p at 30fps with 236mW power cost.
AB - H.264/AVC fractional motion estimation (FME) engine for HDTV 1080p is proposed in this paper. In order to provide real-time processing capability with reasonable hardware cost, several techniques have been presented. Firstly, the H.264/AVC is optimized and only 1 reference frame and block modes above 8 × 8 are supported. Therefore, the computation is reduced to 11.4% and the PSNR loss is only 0.1dB. Secondly, the lossless inside-mode and cross-mode reusing techniques are adopted, which can reduce about 65% pixel generation and SATD calculation. Thirdly, the lossless optimized FME scheduling is used to remove the pipeline bubbles between adjacent 1/2-pel and 1/4-pel FME. The proposed FME engine is realized with TSMC 0.18μm 1P6M CMOS technology and costs 203.2K gates and 52.8KB SRAM. Under 200MHz frequency, the proposed FME engine can real-time encode HDTV 1080p at 30fps with 236mW power cost.
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U2 - 10.1109/SIPS.2007.4387600
DO - 10.1109/SIPS.2007.4387600
M3 - Conference contribution
AN - SCOPUS:47949110913
SN - 1424412226
SN - 9781424412228
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 509
EP - 514
BT - 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings
T2 - 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007
Y2 - 17 October 2007 through 19 October 2007
ER -