TY - GEN
T1 - Hardware Trojan detection and classification based on steady state learning
AU - Oya, Masaru
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/19
Y1 - 2017/9/19
N2 - In this paper, we propose a logic-testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-term random circuit operation. Hence it is very natural that we learn steady signal-transition states of every suspicious Trojan net in a netlist by performing short-term random simulation. After that, we simulate or emulate the netlist in a very long time by giving random test patterns and obtain a set of signal-transition states. By discovering correlation between them, our method detects HTs and finds out its behavior. Experimental results demonstrate that our method can successfully identify all the real Trojan nets to be Trojan nets and all the normal nets to be normal nets, while other existing logic-testing HT detection methods cannot detect some of them.
AB - In this paper, we propose a logic-testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-term random circuit operation. Hence it is very natural that we learn steady signal-transition states of every suspicious Trojan net in a netlist by performing short-term random simulation. After that, we simulate or emulate the netlist in a very long time by giving random test patterns and obtain a set of signal-transition states. By discovering correlation between them, our method detects HTs and finds out its behavior. Experimental results demonstrate that our method can successfully identify all the real Trojan nets to be Trojan nets and all the normal nets to be normal nets, while other existing logic-testing HT detection methods cannot detect some of them.
KW - Gate-level netlist
KW - Hardware Trojans
KW - Logic test
KW - Signal transition
KW - Steady state
UR - http://www.scopus.com/inward/record.url?scp=85032736146&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85032736146&partnerID=8YFLogxK
U2 - 10.1109/IOLTS.2017.8046225
DO - 10.1109/IOLTS.2017.8046225
M3 - Conference contribution
AN - SCOPUS:85032736146
T3 - 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017
SP - 215
EP - 220
BT - 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017
Y2 - 3 July 2017 through 5 July 2017
ER -