High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

N. Takenaka; M. Segawa; T. Uehara; S. Akamatsu; M. Matsumoto; K. Kurimoto; T. Ueda; H. Watanabe; T. Matsutani; K. Yoneda; A. Koshio; Y. Kato; M. Inuishi; T. Oashi; K. Tsukamoto

High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

N. Takenaka^*, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto

^*この研究の対応する著者

研究成果: Conference article › 査読

11 被引用数 (Scopus)

抄録

A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm² and SRAM cell size of 2.77 μm² on the same die.

本文言語	English
ページ（範囲）	62-63
ページ数	2
ジャーナル	Digest of Technical Papers - Symposium on VLSI Technology
出版ステータス	Published - 2000 1月 1
外部発表	はい
イベント	2000 Symposium on VLSI Technology - Honolulu, HI, USA 継続期間: 2000 6月 13 → 2000 6月 15

ASJC Scopus subject areas

電子工学および電気工学

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フィンガープリント

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引用スタイル

Takenaka, N., Segawa, M., Uehara, T., Akamatsu, S., Matsumoto, M., Kurimoto, K., Ueda, T., Watanabe, H., Matsutani, T., Yoneda, K., Koshio, A., Kato, Y., Inuishi, M., Oashi, T., & Tsukamoto, K. (2000). High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization. Digest of Technical Papers - Symposium on VLSI Technology, 62-63.

Takenaka, N, Segawa, M, Uehara, T, Akamatsu, S, Matsumoto, M, Kurimoto, K, Ueda, T, Watanabe, H, Matsutani, T, Yoneda, K, Koshio, A, Kato, Y, Inuishi, M, Oashi, T & Tsukamoto, K 2000, 'High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization', Digest of Technical Papers - Symposium on VLSI Technology, pp. 62-63.

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title = "High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization",

abstract = "A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.",

author = "N. Takenaka and M. Segawa and T. Uehara and S. Akamatsu and M. Matsumoto and K. Kurimoto and T. Ueda and H. Watanabe and T. Matsutani and K. Yoneda and A. Koshio and Y. Kato and M. Inuishi and T. Oashi and K. Tsukamoto",

year = "2000",

month = jan,

day = "1",

language = "English",

pages = "62--63",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 Symposium on VLSI Technology ; Conference date: 13-06-2000 Through 15-06-2000",

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TY - JOUR

T1 - High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

AU - Takenaka, N.

AU - Segawa, M.

AU - Uehara, T.

AU - Akamatsu, S.

AU - Matsumoto, M.

AU - Kurimoto, K.

AU - Ueda, T.

AU - Watanabe, H.

AU - Matsutani, T.

AU - Yoneda, K.

AU - Koshio, A.

AU - Kato, Y.

AU - Inuishi, M.

AU - Oashi, T.

AU - Tsukamoto, K.

PY - 2000/1/1

Y1 - 2000/1/1

N2 - A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.

AB - A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.

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M3 - Conference article

AN - SCOPUS:0033715433

SN - 0743-1562

SP - 62

EP - 63

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2000 Symposium on VLSI Technology

Y2 - 13 June 2000 through 15 June 2000

ER -