A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.
|ジャーナル||Digest of Technical Papers - Symposium on VLSI Technology|
|出版ステータス||Published - 2000 1月 1|
|イベント||2000 Symposium on VLSI Technology - Honolulu, HI, USA|
継続期間: 2000 6月 13 → 2000 6月 15
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