High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Akira Ohchi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1109/VDAT.2008.4542438

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Akira Ohchi^*, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

^*この研究の対応する著者

基幹理工学部

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

本文言語	English
ホスト出版物のタイトル	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
ページ	164-167
ページ数	4
DOI	https://doi.org/10.1109/VDAT.2008.4542438
出版ステータス	Published - 2008 9月 5
イベント	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan, Province of China 継続期間: 2008 4月 23 → 2008 4月 25

出版物シリーズ

名前	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
国/地域	Taiwan, Province of China
City	Hsinchu
Period	08/4/23 → 08/4/25

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

文献へのアクセス

10.1109/VDAT.2008.4542438

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引用スタイル

Ohchi, A., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2008). High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 164-167). 記事 4542438 (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT). https://doi.org/10.1109/VDAT.2008.4542438

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. / Ohchi, Akira; Togawa, Nozomu ; Yanagisawa, Masao その他.
2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 164-167 4542438 (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

研究成果: Conference contribution

Ohchi, A, Togawa, N , Yanagisawa, M & Ohtsuki, T 2008, High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. in 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT., 4542438, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, pp. 164-167, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, Hsinchu, Taiwan, Province of China, 08/4/23. https://doi.org/10.1109/VDAT.2008.4542438

@inproceedings{fad84046c2614e57913832072993822e,

title = "High-level synthesis algorithms with floorplaning for distributed/shared- register architectures",

abstract = "In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.",

author = "Akira Ohchi and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",

year = "2008",

month = sep,

day = "5",

doi = "10.1109/VDAT.2008.4542438",

language = "English",

isbn = "9781424416172",

series = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",

pages = "164--167",

booktitle = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",

note = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT ; Conference date: 23-04-2008 Through 25-04-2008",

}

TY - GEN

T1 - High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

AU - Ohchi, Akira

AU - Togawa, Nozomu

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 2008/9/5

Y1 - 2008/9/5

N2 - In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

AB - In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

UR - http://www.scopus.com/inward/record.url?scp=50649120636&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50649120636&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2008.4542438

DO - 10.1109/VDAT.2008.4542438

M3 - Conference contribution

AN - SCOPUS:50649120636

SN - 9781424416172

T3 - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

SP - 164

EP - 167

BT - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

T2 - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Y2 - 23 April 2008 through 25 April 2008

ER -

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

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出版物シリーズ

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