High-performance 0.5μm transistors

Sixteen-megabit dynamic RAMs (DRAMs) and four-megabit static RAMs (SRAMs) require a 0.5μm design rule to achieve a high integration scale. Along with such integration, 0.5μm devices have to achieve improved performance including high operating speed in circuits. However, submicron MOS transistors suffer from hot-carrier degradation and the short-channel effect. We have used the Mitsubishi Process Simulator (MIPS) and the Mitsubishi Device Simulation Program (MIDSIP) to clarify the internal state of 0.5μm transistors under operation to solve these problems and to develop 0.5μm transistors with improved electrical characteristics. The NMOS transistor features a lightly doped drain and the PMOS a buried-channel transistor.